Table of Contents

• Purpose
• Task 1
  • Writing our first configuration file
  • Goals
  • Resources
• Task 2
  • 1 Bit Binary Adder
  • Massive Parallel outputs
  • Goals
  • Resources
• Task 3
  • Binary Counter /2n
  • USB Interfacing
  • Goals
  • Resources
• Auxiliary Information
  • Our Setup
  • Learning Verilog
  • FPGA Slice Components
  • Informative links

Purpose

• Use of an Field-Programmable Gate Array (FPGA) is a good way to learn about complex digital circuits, and this is the main goal of this segment of the course.
• The process of building a complex circuit of logic gates can be tedious: power and ground lines need to be in place; myriad connections among the multi-gate chip need to be routed properly; timing issues can arise from propagation delays; making changes are not easy; hand-wired circuits will be slow; printed circuit board designs take time to create and are not easy to change. An FPGA is a collection of digital logic elements which can be configured with a hardware description language. Timing issues are easier to handle, and circuits can be very fast. Nary a single interconnection wire is required.
• FPGAs provide new capabilities for advanced laboratory instrumentation and for commercial products ranging from hand-held devices to large radar arrays. So, an introduction to FPGAs will help students engaged in experimental research and will be an important addition to the skill set that employers seek.

Task 1

The first task is an introduction to FPGAs, Xilinx ISE, Verilog, and Opal Kelly FrontPanel. First we need to learn what we are dealing with. Below is a wealth of supplementary information about what an FPGA is, and how Verilog works.

Writing our first configuration file

• Read Chapters 1 and 2 of the Verilog walkthrough listed at the bottom of the page. Pay attention to {Scopes, Modules, types, reg, wire}
• Create a new Xilinx ISE project for the specific FPGA being used
• Construct a Verilog module to implement one of {AND,OR,XOR} primitives. This includes declaring the module, its inputs/outputs(IOs), and type-casting them properly. Then you will need to attach the inputs to an output via one of the above mentioned primitive constructs.
• Constrain it to your project with a Universal Constraints File (.ucf). This is what actually ties the abstractly written Verilog to the physical FPGA via pin declarations (and more).
• Generate a .bit file to transfer
• Use Opal Kelly FrontPanel to transfer (extra 'cool points' for using python instead)
• Verify results (with truth table)
• Repeat process using Boolean operators {&,|,^} and compare results to primitives
• Using whichever type of logical comparison is better, create a configuration that allows the FPGA to select which logical operation to use based on user input

Goals

(Details Tuesday)

• Measure the propagation delay of an {AND,OR,XOR} gate primitive
• Measure the delay in a Boolean implementation of the same gate
• Save a working copy of your code, with comments describing what you have done well enough that someone who does not know your goal in this code could learn it easily
• Write a small summary report of this task

Resources

• logic.v
• global_params.v
• xem6001.ucf

Task 2

This task will be an exploration of more complex Boolean behavior of the FPGA. Here we will explore what an adder is, and how to implement it in Verilog, as well as on the FPGA. Then we will introduce the concept of Static Ram (SRAM) and will build 2 bits of SRAM to incorporate into our FPGA design.

1 Bit Binary Adder

A 1 bit binary adder takes a number of inputs (usually two) and adds the binary (1 or 0) values together, producing an output in binary of the summation.

• Design on paper, electronically or otherwise) a schematic for a 1 bit binary adder
• Construct a Xilinx project with a module implementing your design
• Write down and Verify your truth table
• Now, repeat the process for designing and implementing a 2-bit adder

Massive Parallel outputs

• Design and implement the fastest possible output signal on your FPGA
• Utilize the parallel nature of the FPGA and implement this on every available port
• Capture information about 2 of the signals and compare relative phase and amplitudes

Goals

• Design schematics for {1,2} bit adder
• Generate Xilinx projects for your schematics, and implement with lots of commenting
• Generate an output signal at the fastest possible output rate on the FPGA
• Generate the fastest output signal across all bus pins on the FPGA (JP2 xbus,JP3 ybus)
• Write a short summary of each project; what it is, how it works, what obstacles you had

Resources

• A Working 2bit adder to be used for reference. Check this out only if you are stuck on your implementation.

Task 3

We will now begin our investigation of higher level FPGA functionality. To start, we'll create a binary counter, which is a very useful divide by 2n concept. Then we will move into discovery and perturbation of an existing USB implementation protocol, and python capturing script.

Binary Counter /2n

• Be present and attentive for a discussion on Binary counters and higher level implementation in verilog, during class
• Design and implement an 8 bit Binary counter in Verilog
• Demonstrate control of the counter by slowing it down to human readable scales
• Implement a "pause" condition for the counter, so that a static output can be temporarily viewed

USB Interfacing

• Not to be performed. If you have personal ambitions or questions on how to do this, see John Elliott for further information.

Goals

• Design a procedural function that outputs a binary counter (divide by 2n)
• Control the clock rate of the counter
• Utilize large USB configuration file, by outputting results of counter onto PC (verify counting)
• Write a short summary of the process for each element of the task including obstacles, methodology, and performance limits of the procedural assignments verses the continuous (primitive gate) assignments.

Resources

• USB in a nutshell A guide to USB 2.0 specification

Auxiliary Information

Our Setup

• Opal Kelly XEM6001 This is the FPGA Evaluation board that will be used in the course
• Xilinx ISE Our FPGA is built by this company, and thus we use their Integrated Development Environment (IDE)

Learning Verilog

• Complete Verilog Walkthrough A complete A-Z walkthrough on the history, structure, nature, and syntax of verilog hardware description language

FPGA Slice Components

• XOR Gate The XOR gate is often used to form binary functional completeness, in combination with Look Up Tables (LUTs).
• Flip-Flop Flip-flops are a main component of FPGAs. They are used for timing, event triggering, buffering, shifting, and much much more.
• Multiplexer Used to select inputs and in combination with LUTs to provide dynamic truth tables.
• Look up Table A typical slice contains several lookup tables to create dynamic truth table results for the FPGA implementation.
• Full Adder A full adder is generally present in a (or as its own) slice

Informative links

• Functional Completeness The wiki on functional completeness, the core idea behind the construction of FPGA slices. In a nutshell a small set of logical operations can be used to form a complete set of logic and truth tables.
• Field Programmable Gate Arrays The history, development, and application of FPGAs. This is a good starting point to get more eclectic information on the FPGA than the scope of this course offers.